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중앙대학교 창의ICT공과대학 전자전기공학부

논문[95]

#95. A 2.5 GS/s 7-Bit 5-Way Time-Interleaved SAR ADC With On-Chip Background Offset and Timing-Skew Calibration

2022.10 · IEEE Transactions on Circuits and Systems II: Express Briefs

(DOI) https://doi.org/10.1109/TCSII.2022.3188290

#94. A 2.5 GHz 104 mW 57.35 dBc SFDR Non-linear DAC-based Direct-Digital Frequency Synthesizer in 65 nm CMOS Process

2022.9

(DOI) https://doi.org/10.1109/ESSCIRC55480.2022.9911334

프로시딩[13]

#13. A 2.5 GHz 104 mW 57.35 dBc SFDR Non-linear DAC-based Direct-Digital Frequency Synthesizer in 65 nm CMOS Process

2022.9.19:241-244

(DOI) https://doi.org/10.1109/ESSCIRC55480.2022.9911334

#12. A SAR ADC with Segment Binary Weighted Attenuation Capacitor DAC layout technique

2021.10.06:389-390

(DOI) https://doi.org/10.1109/ISOCC53507.2021.9614025