ResearchWho?

김태환

교수

서울대학교 공과대학 전기·정보공학부

논문[96]

#96. Improving Performance and Power by Co-Optimizing Middle-of-Line Routing, Pin Pattern Generation, and Contact over Active Gates in Standard Cell Layout Synthesis

2022.8

(DOI) https://doi.org/10.1145/3531437.3539712

#95. Tightly Linking 3D Via Allocation Towards Routing Optimization for Monolithic 3D ICs

2022.8

(DOI) https://doi.org/10.1145/3531437.3539714

프로시딩[74]

#74. Optimizing Timing in Placement Through I/O Signal Flipping on Multi-bit Flip-flops

2022.5.27:2623-2624

(DOI) https://doi.org/10.1109/ISCAS48785.2022.9937267

#73. Selective Clock Gating Based on Comprehensive Power Saving Analysis

2022.5.27:230-231

(DOI) https://doi.org/10.1109/ISCAS48785.2022.9937589