ResearchWho?
    • Profile Image
    박관서
    Position 겸임교수
    Current Department 연세대학교(신촌) 공과대학 시스템반도체공학과
    프로필
    연구 성과
    논문[22]
    #22. Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector
    Journal Information 2022.10 · IEEE Journal of Solid-State Circuits
    Identifier (DOI) https://doi.org/10.1109/JSSC.2022.3189663
    #21. Design Techniques for a 6.4–32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency–Phase Detector
    Journal Information 2022.2 · IEEE Journal of Solid-State Circuits
    Identifier (DOI) https://doi.org/10.1109/JSSC.2021.3116485
    발표[14]
    #14. A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology
    Organization 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
    Date 2022.6
    #13. 8 An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS
    Organization 2021 IEEE International Solid- State Circuits Conference (ISSCC)
    Date 2021.2
    팔로우 추천