ResearchWho?
    • Profile Image
    최재혁
    Position Associate Professor
    Current Department 한국과학기술원 공과대학 전기및전자공학부
    프로필
    연구 성과
    논문[78]
    #78. A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping Δ Σ M
    Journal Information 2022.9 · IEEE Journal of Solid-State Circuits 57(9):1-1
    Identifier (DOI) https://doi.org/10.1109/JSSC.2022.3141782
    #77. An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector
    Journal Information 2022.9 · IEEE Journal of Solid-State Circuits
    Identifier (DOI) https://doi.org/10.1109/JSSC.2021.3123156
    발표[55]
    #55. An Ultra-Low Integrated-Phase-Noise 28-GHz LO Generator for 5G Transceivers Supporting Multiple Frequency Bands
    Organization 2022 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)
    Date 2022.8
    #54. A 0.0084-mV-FOM, Fast-Transient and Low-Power External-Clock-Less Digital LDO Using a Gear-Shifting Comparator for the Wide-Range Adaptive Sampling Frequency
    Organization ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)
    Date 2021.9
    특허[15]
    #15. 인젝션 락킹 기반 링오실레이터의 피브이티 변화 교정을 위한 장치 및 방법
    Identifier [출원] 10-2013-0111911
    Patent Country 대한민국
    #14. 지연 고정 루프 회로 기반의 위상 생성기 및 위상 생성 방법
    Identifier [출원] 10-2014-0194798
    Patent Country 대한민국
    팔로우 추천