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겸임교수

성균관대학교 정보통신대학 반도체시스템공학과

논문[22]

#22. Pinning Page Structure Entries to Last-Level Cache for Fast Address Translation

2022.10.26 · IEEE Access

(DOI) https://doi.org/10.1109/access.2022.3217484

#21. On-the-Fly Lowering Engine: Offloading Data Layout Conversion for Convolutional Neural Networks

2022.7.20 · IEEE Access · 10:79730-79746

(DOI) https://doi.org/10.1109/ACCESS.2022.3192618

프로시딩[13]

#13. Virtual PTE Storage: Repurposing Last-level Cache to Accelerate Address Translation for Big Data Workloads

2022.10.26:1-5

(DOI) https://doi.org/10.1109/ICCE-Asia57006.2022.9954665

#12. Proactive Dead Block Eviction for Reducing Write Latency in STT-MRAM Caches

2021.1.31:1-2

(DOI) https://doi.org/10.1109/ICEIC51217.2021.9369729